CMP0817BA0-I cmos lpram revision 0.2 aug. 2006 1 document title 512k x 16 bit super low power and low voltage full cmos ram revision history final oct. 26 th , 2005 added g(pb-free) and h(pb-free & halogen free) descriptions 0.1 final aug. 22 nd , 2006 removed 60ns descriptions 0.2 final may. 2 nd , 2004 initial draft 0.0 remark draft date history revision no.
CMP0817BA0-I cmos lpram revision 0.2 aug. 2006 2 512k x 16 bit super low power and low voltage full cmos ram pin description 1 2 3 4 5 6 a b c d e f g h /lb /oe a0 a1 a2 i/o9 /ub a3 a4 /cs i/o10 i/o11 a5 a6 i/o2 vss i/o12 a17 a7 i/o4 vccq i/o13 dnu a16 i/o5 i/o15 i/o14 a14 a15 i/o6 i/o16 nc a12 a13 /we a18a8a9a10a11 cs2 i/o1 i/o3 vcc vss i/o7 i/o8 nc 48-fbga : top view(ball down) do not use dnu data inputs/outputs i/o1~i/o16 core power vcc chip select input cs2 no connection nc lower byte(i/o 1~8) /lb address inputs a0~a18 upper byte(i/o9~16) /ub write enable input /we ground vss output enable input /oe i/o power vccq chip select input /cs1 function name function name features ? process technology : full cmos ? organization : 512k x 16 ? power supply voltage : 2.7~3.3v ? three state output and ttl compatible ? package type : 48-fbga-6.00x8.00 mm 2 ? separated i/o power(vccq) & core power(vcc) ? easy memory expansion with /cs1, cs2, and /oe features ? automatic power-down when deselected product family isb1 (cmos standby current) icc2 icc1 max. typ. 20ma max. typ. max. typ. min. 70ua 3.0 typ. max. 30ua 12ma 3ma 1.5ma 70ns 3.3 2.7 industrial (-40~85?c) cmp0817ba0- f 70i operating voltage (v) f = fmax f = 1mhz power dissipation speed operating temperature product family functional block diagram precharge circuit. clk gen. vcc vss memory array row addresses i/o circuit column select data cont data cont column addresses data cont control logic /cs1 cs2 /oe /we /ub /lb i/o9~i/o16 i/o1~i/o8 row select 1. typical values are included for reference only and are not guaranteed or tested. typical values are measured at vcc = vcc ( typ) and t a = 25c. 2. f =fbga, g =fbga(pb-free), h =fbga(pb-free & halogen free), w =wafer
CMP0817BA0-I cmos lpram revision 0.2 aug. 2006 3 product list 48-fbga, 70ns, vcc=3.0v, vccq=3.0v(2.5v,1.8v) cmp0817ba0- f 70i function part name industrial temperature products(-40~85?c) functional description active word write din din l l active upper byte write din high-z l h active lower byte write high-z din h l l x 1) active word read dout dout l l active upper byte read dout high-z l h active lower byte read high-z dout h l h l h l active output disabled high-z high-z l x 1) h h h active output disabled high-z high-z x 1) l h h h l standby deselect/power-down high-z high-z h h x 1) x 1) h x 1) standby deselect/power-down high-z high-z x 1) x 1) x 1) x 1) l x 1) standby deselect/power-down high-z high-z x 1) x 1) x 1) x 1) h h power mode i/o9-16 i/o1-8 /ub /lb /we /oe cs2 /cs1 1. x means don?t care.(must be low or high state) absolute maximum ratings 1) ?c -40 to 85 t a operating temperature ?c -65 to 150 t stg storage temperature w 1.0 p d power dissipation v -0.2 to 3.6 vcc voltage on vcc supply relative to vss v -0.2 to vcc+0.3v v in , v out voltage on any pin relative to vss unit ratings symbol item 1. stresses greater than those listed under ?absolute maximum ratings? may cause perm anent damage to the device. functional operation should be restricted to recommended operating condition. exposure to absolute maximum rating conditions for industria l periods may affect reliability. recommended dc operating conditions 1) -0.2 3) 0.8vccq 0 2.7 2.7 min cmp0817ba0 0.2vccq vcc+0.2 2) 0 3.3 3.3 max -0.2 3) 0.8vccq 0 2.25 2.7 min 0.2vccq vcc+0.2 2) 0 2.75 3.3 max 1.95 v 3.3 2.7 v cc supply voltage 0.2vccq vcc+0.2 2) 0 max v -0.2 3) v il input low voltage v 0.8vccq v ih input high voltage v 0 v ss ground v 1.65 v ccq i/o operating voltage (vccq vcc) unit min symbol item note : 1.t a =-40 to 85?c, otherwise specified. 2. overshoot : vcc+1.0v in case of pulse width 20ns. 3. undershoot : -1.0v in case of pulse width 20ns. 4. overshoot and undershoot are sampled, not 100% tested. 1. f =fbga, g =fbga(pb-free), h =fbga(pb-free & halogen free), w =wafer
CMP0817BA0-I cmos lpram revision 0.2 aug. 2006 4 dc and operating characteristics 1. capacitance is sampled, not 100% tested. capacitance 1) (f=1mhz , t a =25?c) 8 8 max - - min pf v io =0v c io input/output capacitance pf v in =0v c in input capacitance unit test condition symbol item ua 70 - - /cs v cc -0.2v, cs2 0.2v, other inputs=0~v cc i sb1 standby current(cmos) ua 1 - -1 /cs=v ih , cs2=v ih , /oe=v ih or /we=v il , v io =v ss to v cc i lo output leakage current ua 1 - -1 v in =v ss to v cc i li input leakage current ma 3 1.5 - cycle time=1us, 100%duty, i io =0ma, /cs 0.2v, cs2=v ih , v in 0.2v or v in v cc -0.2v i cc1 average operating current v 0.2vccq i ol =0.5ma v ol output low voltage ma 25 15 - cycle time=min, i io =0ma, 100% duty, /cs=v il , cs2=v ih , v in =v il or v ih i cc2 v 0.8vccq i oh =-0.5ma v oh output high voltage 0.3 max - typ - min ma /cs=v ih , cs2=v ih , other inputs=v ih or v il i sb standby current(ttl) unit test conditions symbol item
CMP0817BA0-I cmos lpram revision 0.2 aug. 2006 5 ac operating conditions test conditions (test load and input/output reference) input pulse level : 0.2 to vcc-0.2v input rising and falling time : 5ns input and output reference voltage : 0.5*vccq output load(see right) : c l =30pf+1ttl ac characteristics (v cc =2.7v~3.3v, industrial product : t a =-40 to 85?c) 30pf 1ttl 1. /cs high pulse width is defined by /cs or (/ub and /lb) because /ub & /lb can make standby mode when /ub=high and /lb=high. ns - 10 tcp /cs high pulse width 1) ns - 5 tow end write to output low-z ns - 0 tdh data hold from write time ns - 20 tdw data to write time overlap ns 5 0 twhz write to output high-z ns - 0 twr write recovery time ns - 50 twp write pulse width ns - 60 tbw /ub, /lb valid to end of write ns - 60 taw address valid to end of write ns - 0 tas address set-up time ns - 60 tcw chip select to end of write ns 80k 70 twc write cycle time write ns - 5 toh output hold from address change ns 5 0 tohz output disable to high- z output ns 5 0 tbhz /ub, /lb disable to high- z output ns 5 0 thz chip disable to high- z output ns - 5 tolz output enable to low-z output 70ns ns - 10 tblz /ub, /lb enable to low-z output ns - 10 tlz chip select to low-z output ns 70 - tba /ub, /lb access time ns 25 - toe output enable to valid output ns 70 - tco chip select to output ns 70 - taa address access time ns 80k 70 trc read cycle time read max min units symbol parameter list
CMP0817BA0-I cmos lpram revision 0.2 aug. 2006 6 read cycle (1) (address controlled,/cs1=/oe=v il , cs2=/we=v ih , /ub or/and /lb=v il ) address data out trc previous data valid data valid taa toh read cycle (2) (cs2=/we=v ih ) address taa tco toh thz /cs1 trc 1. thz and tohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. at any given temperature and voltage condition, thz(max.) is less than tlz(min.) both for a given device and from device to device interconnection. 3. do not access device with cycle timing shorter than trc(twc) for continuous periods > 80us. tba toe tolz tblz tlz data valid high-z tbhz tohz /ub, /lb /oe data out cs2
CMP0817BA0-I cmos lpram revision 0.2 aug. 2006 7 write cycle (1) (/we controlled) address /cs1 /ub, /lb /we data out twc tcw(2) twr(4) taw tbw twp(1) tas(3) high-z high-z data undefined data valid tdw tdh tow twhz data in cs2 write cycle (2) (/cs1 controlled) address /cs1 /ub, /lb /we data out twc twr(4) tbw twp(1) high-z high-z data valid tdw tdh data in tcw(2) tas(3) taw cs2 write cycle (3) (cs2 controlled) address /cs1 /ub, /lb /we data out twc twr(4) tbw twp(1) high-z high-z data valid tdw tdh data in tcw(2) taw tas(3) cs2
CMP0817BA0-I cmos lpram revision 0.2 aug. 2006 8 1. a write occurs during the overlap (twp) of low /cs and /we. a write begins when /cs goes low and /we goes low with asserting /ub or /lb for single byte operation or simultaneously asserting /ub and /lb for double byte operation. a write ends at the earliest transition when /cs goes high and /we goes high. the twp is measured from the beginning of write to the end of write. 2. tcw is measured from the /cs going low to end of write. 3. tas is measured from the address valid to the beginning of write. 4. twr is measured from the end of write to the address change. twr applied in case a write ends as /cs or /we going high. 5. do not access device with cycle timing shorter than trc(twc) for continuous periods > 80us. write cycle (4) (/ub, /lb controlled) address /cs1 /ub, /lb /we data out twc twr(4) tbw twp(1) high-z high-z data valid tdw tdh data in tcw(2) taw tas(3) cs2
CMP0817BA0-I cmos lpram revision 0.2 aug. 2006 9 package dimension 48 ball fine pitch bga (0.75mm ball pitch) top view b c #a1 bottom view side view detail a unit : millimeters 0.08 - - y 0.30 0.25 0.20 e2 - 0.75 - e1 - 1.00 - e 0.40 0.35 0.30 d - 5.25 - c1 8.10 8.00 7.90 c - 3.75 - b1 6.10 6.00 5.90 b - 0.75 - a max typ min - d c e2 e e1 0.30 0.85/typ. 0.25/typ. y notes. 1. bump counts : 48(8row x 6column) 2. bump pitch : (x,y)=(0.75 x 0.75)(typ.) 3. all tolerance are +/-0.050 unless otherwise specified. 4. typ : typical 5. y is coplanarity : 0.08(max) b c b/2 b1 0.05 0.05 a1 index mark 6 5 4 3 2 1 a b c d c1/2 c1 e f g h a
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